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Active FPGA stable power sequencing solution -2

Power off controlUsing a circuit with a known time constant to actively discharge the decoupling capacitor, 

the sequencer can maintain the correct power-down sequence by temporarily inserting the discharge resistor into the series capacitor.

Below picture shows how to insert a resistor into the circuit using a carefully selected pair of MOSFETs with the minimum of the required components.

The EN output of the power sequencer is connected to the Enable pin of the DC-DC regulator and to the gate of the P-channel MOSFET (Q1). 

Sequencer Output Decreasing Q1 When the DC-DC regulator is deactivated, Q1 inverts the signal and turns on N-channel MOSFET Q2. 

When turned on, Q2 discharges the 15mF decoupling capacitor to ground through the R2 resistor.                       

The above circuit assumes that the DC-DC regulator can not continuously generate output after it provides a shutdown signal. 

If the output of the DC-DC regulator continues to supply power after it receives a shutdown command, an additional relay is required to activate the discharge circuit.

The R2 value chosen must ensure proper discharge time, allowing the sequencer to shut down within an acceptable time interval. 

Also note that the resistor must be large enough to avoid excessive current spikes, avoid EMI problems, and create transient thermal stresses on the Q2 and decoupling capacitor banks. 

In practice, there are additional important parameters to consider when choosing R2, such as the on-resistance of Q2 (RDS (ON)) and the equivalent series resistance (ESR) of the capacitor bank.

The MOSFET Q1 should be referenced to the power sequencer output voltage threshold. 

The chosen device should have a high gate-to-gate voltage (VGS (th)) to ensure that the sequencer output stays off when the output is high, but be aware that VGS (th) will increase as the junction temperature rises decline.

The sequence generator operation selected in this example operates with a supply voltage of 5V and a minimum specified high potential output voltage of 4.19V. 

Q1's VGS (th) must be greater than 0.9V at 60 ° C ambient operating temperature to ensure proper operation.

In addition, the gate should be pulled down to the source potential using a 100kΩ resistor to avoid false opening. 

View the normalized VGS (th) versus temperature graph in the MOSFET datasheet showing that the Diodes ZXMP6A13F meets the specifications: a guaranteed minimum VGS (th) of 1V at room temperature and a drop of about 0.9V at 60 ° C.

In this example, we assume that the sequencer must turn off a total of 10V of rails within 100ms. 

Therefore, the decoupling capacitor bank of each rail must be discharged within 10ms. 

The goal is to achieve 3 times the RC time constant of 8ms, ensuring that the capacitor discharges below 5% of full voltage for the required time.  

When calculating RC constants, the capacitor bank RDS (ON), parasitic line resistance, and ESR must all be taken into account with resistor R2.

Assuming that the ESR of the capacitor and the line resistance do not add up to 10 mΩ and the total decoupling capacitor bank has a capacitance of 15 mF, the appropriate values of RDS (ON) and R2 can be found by the following expressions:3 x (10mΩ + R2 + (1.5 x RDS(ON))) x 15mF = 8msAssuming R2 = 50mΩ, the RDS (ON) of power MOSFET Q2 must be less than 80mΩ at VGS = 4.5V and at an ambient temperature of 25˚C.

The effects of temperature-dependent variations and bulk variations of RDS (ON) should also be taken into account when selecting MOSFETs. RDS (ON) With a 4.5V gate drive, variations outside the expected operating temperature range may be as high as 15mΩ. 

Therefore, it is best practice to determine that R2 is about twice as large as the maximum RDS (ON) specified by the manufacturer of the selected MOSFET.

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