Active FPGA stable power sequencing solution -1

Ensuring multiple FPGA rails are shut down in the correct sequence is as important as ensuring that the power-on sequence is correct,

preventing the unit from prematurely failing due to a voltage condition that can not be determined.Power sequencing safety considerations.

When launching the multiple rails of today's large system-on-a-chip FPGAs,

there are many techniques that can be used to control their startup sequence and timing.

It is important to follow the correct sequence specified by the device manufacturer so that excessive current drawn by the device can be avoided resulting in damage. Some methods control the Enable pin of the next supply in the sequence by manipulating the power good output of each converter.

please insert a capacitor, If you need a relay.

Another similar approach is to use the reset IC to start the next converter after the previous supply has reached the required voltage.

Each method has some disadvantages, and none of these methods control the order in which the power is turned off.

Closing the rail in the correct reverse order is as important as turning on the power in the correct sequence to ensure that the unit operates safely.

Using a dedicated power sequencing IC, it is more stable to ensure that the order is correct.

The IC can be programmed to send Enable signals at the desired time points.Below picture shows how a multichannel sequencer manages FPGA core logic, perimeter, and I / O domains.

Even so, the power-down sequence is still difficult to control because the decoupling capacitors on each rail may still have residual charge after the converter is turned off, and the residual time may not be constant, and up to 20mF of total can be connected per rail Coupling capacitance.   

more details will be show on :Active FPGA stable power sequencing solution -2       

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